# Port on RISC-V architecture (QEMU/board)

**URL:** <http://discourse.heig-vd.ch/t/port-on-risc-v-architecture-qemu-board/217>\
**Category:** SO3 Operating System\
**Created:** [June 1, 2021, 8:01am UTC](http://discourse.heig-vd.ch/t/port-on-risc-v-architecture-qemu-board/217 "2021-06-01T08:01:04Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![rossierd](http://discourse.heig-vd.ch/user_avatar/discourse.heig-vd.ch/rossierd/32/4_2.png) [@rossierd](http://discourse.heig-vd.ch/u/rossierd)\
**Post date:** [June 1, 2021, 8:01am UTC](http://discourse.heig-vd.ch/t/port-on-risc-v-architecture-qemu-board/217/1 "2021-06-01T08:01:04Z")

</div>

A port of SO3 on RISC-V architecture is ongoing by Nicolas Müller.  
A first port will be achieved in QEMU/virt environment and we expect to have  
a deployment on a board as well.